This invention relates to a semiconductor device and, in particular, to a semiconductor device using a phase change material as a memory element of a memory cell and a method of producing the same.
A phase change memory using a phase change material is known in the art. As the phase change material, a chalcogenide material (GeSbTe) is generally used. A change in resistance value following a change in crystal structure of the chalcogenide material is used as memory information. In the phase change memory, a chalcogenide layer obtained by depositing the chalcogenide material is used as a memory element instead of a capacitance element in a typical DRAM (Dynamic Random Access Memory). The chalcogenide layer is varied in crystal structure depending upon a heating temperature and a cooling time and exhibits a high resistance value in an amorphous state and a low resistance value in a crystalline state. In the phase change memory, the crystal structure of the chalcogenide layer is changed and the resistance value consequently changed is used as the memory information.
In order to write the information into the chalcogenide layer, two operations are carried out, i.e., a reset operation and a set operation. In the reset operation, the chalcogenide layer is supplied with sufficient Joule heat to be melted and then rapidly cooled to create an amorphous state exhibiting a high resistance. In the set operation, the chalcogenide layer is supplied with less Joule heat and gradually cooled to create a crystalline state having a face-centered cubic structure exhibiting a low resistance. A heat quantity to be supplied and a cooling rate are controlled by an electric current value and a length (application time) of a pulse applied to the chalcogenide layer. Thus, reading and writing operations as a memory are carried out by changing the crystal structure of the chalcogenide layer to thereby change the resistance value.
The phase change memory using the chalcogenide layer has a basic structure in which the chalcogenide layer is formed on an upper surface of a lower heater electrode and an upper electrode is formed on the chalcogenide layer. Thus, the lower heater electrode and the upper electrode are formed on opposite ends of the chalcogenide layer. By applying an electric voltage between these electrodes, reading and writing operations are carried out.
The phase change memory is disclosed in following patent documents.
Japanese Unexamined Patent Application Publication (JP-A) No. H04-045585 (Patent Document 1) discloses that a chalcogenide layer formed on a lower heater electrode is patterned with an upper electrode used as a mask to form a cylindrical chalcogenide layer having a small diameter.
Japanese Unexamined Patent Application Publication (JP-A) No. 2005-032855 (Patent Document 2) discloses that a lower heater electrode and a chalcogenide layer are formed in one plug for the purpose of consolidation with a standard logic process.
Japanese Unexamined Patent Application Publication (JP-A) No. 2004-349709 (Patent Document 3) discloses that oxide is formed at an interface between a lower heater electrode and a chalcogenide layer in order to increase heat generation of the lower heater electrode.
The present inventors have found a problem that, if the number of times of rewriting is increased in the memory element having each of the above-mentioned structures, reset and set resistance values are varied. When the reset and the set resistance values are varied, an electric current required for rewriting (energy required for rewriting) is increased. In other words, as the number of times of rewriting is increased, rewriting can not be carried out at a predetermined current level so that the number of times of rewriting may not be assured. On the other hand, in the abovementioned patent documents, no recognition is made about such dependency upon the number of times of rewriting and, therefore, no solution is proposed.
As described above, in the above-mentioned memory element using the chalcogenide layer, there is a problem that the resistance value of the chalcogenide layer is varied as the number of times of rewriting is increased. When the resistance value of the chalcogenide layer is varied, an electric current required for rewriting is increased. In other words, as the number of times of rewriting is increased, rewriting can not be carried out at a predetermined current level so that the number of times of rewriting may not be assured.
Concretely, the number of times of rewriting the chalcogenide layer as required in practical use is about 105. However, as the number of times of rewriting is increased, the volume of a phase change region is varied and increased. In this event, rewriting requires a large electric current because the volume to be changed in phase is increased. In other words, rewriting can not be carried out at a predetermined current level. Thus, rewriting resistance or durability is not assured due to an adverse influence caused by a part of the chalcogenide layer which does not act as a phase change region in an early stage of repetition of rewriting operations.